By Himanshu Bhatnagar
Complicated ASIC Chip Synthesis: utilizing Synopsys TM layout CompilerTM actual CompilerTM and PrimeTime TM, moment variation describes the complex suggestions and strategies used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the complete ASIC layout circulation method distinctive for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this e-book is on real-time software of Synopsys instruments, used to strive against numerous difficulties obvious at VDSM geometries. Readers should be uncovered to an efficient layout technique for dealing with advanced, sub-micron ASIC designs. value is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, actual synthesis, and static timing research. At every one step, difficulties relating to each one section of the layout move are pointed out, with suggestions and work-around defined intimately. moreover, an important matters regarding structure, which include clock tree synthesis and back-end integration (links to structure) also are mentioned at size. moreover, the ebook comprises in-depth discussions at the foundation of Synopsys know-how libraries and HDL coding kinds, particular in the direction of optimum synthesis resolution. objective audiences for this ebook are working towards ASIC layout engineers and masters point scholars project complex VLSI classes on ASIC chip layout and DFT thoughts.
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Extra resources for Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime
Also, the clock tree has been inserted in the design by the layout tool. The clock tree insertion modifies the existing structure of the design. In other words, the netlist in the layout tool is different from the original netlist present in DC. This is because of the fact that the design present in the layout tool contains the clock tree, 32 Chapter 2 whereas the original design in DC does not contain this information. Therefore, the clock tree information should somehow be transferred to the design residing in DC or PT.
The design is now ready for routing. In a broad sense, routing is performed in two phases – global route and detailed route. During global route, the router divides the layout surface into separate regions and performs a point-to-point “loose” routing without actually placing the geometric wires. The final routing is performed by the detailed router, which physically places the geometric wires and routes within the regions. Full explanations of these types of routing are explained in Chapter 9.
The architectural specifications define the functionality and partitioning of the chip into several manageable blocks, while the electrical specifications define the relationship between the blocks in terms of timing information. The next phase involves the implementation of these specifications. In the past this was achieved by manually drawing the schematics, utilizing the components found in a cell library. This process was time consuming and was impractical for design reuse. To overcome this problem, hardware description languages (HDL) were developed.
Advanced ASIC chip synthesis: using Synopsys Design Compiler, Physical Compiler, and PrimeTime by Himanshu Bhatnagar