By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

ISBN-10: 3319139053

ISBN-13: 9783319139050

ISBN-10: 3319139061

ISBN-13: 9783319139067

This monograph is predicated at the 3rd author's lectures on machine structure, given in the summertime semester 2013 at Saarland collage, Germany. It encompasses a gate point development of a multi-core desktop with pipelined MIPS processor cores and a sequentially constant shared memory.

The ebook includes the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens how one can the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and hence deterministic. against this the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness evidence of the shared reminiscence on the gate point are the most technical contributions of this work.

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**Extra info for A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof**

**Example text**

One shows by an easy induction on k ∀t ∈ [e(c) + σ, e(c + 1) + ρ] : x[i](t) = x[i]in(e(c)) and ∀k ∈ [1 : K − 1] : ∀t ∈ (e(c + k) + ρ, e(c + k + 1) + ρ] : x[i](t) = x[i]in(e(c)) . For the deﬁnition of the value y(t) of gates g at time t in the detailed model, we distinguish three cases (see Fig. 22): • Regular signal propagation. Here, all input signals are binary and stable for the maximal propagation delay β before t. For inverters y this is captured by the following predicate: reg(y, t) ↔ ∃a ∈ B : ∀t ∈ [t − β, t] : in1(y)(t ) = a .

By straightforward induction, we show that the output of a circuit is welldeﬁned. 2 (well-deﬁned circuit output). Let d(s) = n, then output s(a) of the circuit is well deﬁned. Proof. By induction on n. If n = 0, then s is an input and s(a) is clearly well deﬁned by the ﬁrst rule. If n > 0, then we have d(in1(s)) < n. If s is not an inverter, we also have d(in2(s)) < n. By induction hypothesis in1(s)(a) and in2(s)(a) (for the case if s is not an inverter) are well deﬁned. We now conclude that s(a) is well deﬁned by the second and third rules.

In the jargon of hardware designers this is called the high impedance state or high Z or simply Z. In order to specify behavior and operating conditions of open collector and tristate drivers, we have to permit Z as a signal value for drivers y. Thus, we have y : R → {0, 1, Ω, Z} . For the propagation delay of open collector drivers, we use the same parameters α and β as for gates. Regular signal propagation is deﬁned the same way as for inverters: reg(y, t) ↔ ∃a ∈ B : ∀t ∈ [t − β, t] : yin(t) = a .

### A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

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